The present disclosure relates to semiconductor device fabrication, and more specifically, to source/drain regions with a first epitaxial region having a substantially uniform sidewall thickness.
Conventional integrated circuits, such as microprocessors, storage devices, etc., include millions of circuit elements including structures such as transistors. Transistors come in a variety of shapes and forms, e.g., planar, fin-type, nanowire, etc. Irrespective of the physical configuration of the transistor device, each transistor comprises source/drain regions in a substrate, and a gate structure defining a channel region positioned between the source/drain regions. For example, where the transistor is a FinFET, the gate structure may be formed on the fin, and the source/drain regions may be formed in and/or on portions of the fin not covered by the gate structure. Transistors may be utilized by applying a predetermined control voltage to the gate structure causing the channel region to become conductive below the gate structure and between the source/drain regions. The transistors are generally either an N-type (NFET) or P-type (PFET) transistor device wherein the “N” and “P” indicate the type of dopants used to create the source/drain regions of the devices.
At a later point in integrated circuit fabrication, contact structures are typically formed to the source/drain regions of the transistors for electrical connection thereto. Generally, it is desirable to make the area of the interface between the contact structures and the source/drain regions as large as possible and as exhibiting as low of an electrical resistance as possible. Source/drain region formation may include the growth of epitaxial material to create a larger landing area for contact structures. One conventional method for forming epitaxial material in a source/drain region of a transistor is referred to as an “embedded epi.” Forming an “embedded” epitaxial material may include removing an upper portion of the source/drain region of the transistor (e.g., an upper portion of the fin in a FinFET), and growing epitaxial material therein. The formation may include growing a single embedded epitaxial material region, or multiple embedded epitaxial material regions with different dopant concentrations from the source/drain regions.
One challenge associated with forming an “embedded” epitaxial material may include contact resistance reduction and performance degradation where a single embedded epitaxial material with a high concentration of dopant is formed. Another challenge associated with forming an “embedded” epitaxial layer may include increased contact resistance and degradation of performance where a first embedded epitaxial region with a low concentration of dopant is formed thinly on fins in the source/drain regions near the gate structure.